Jens Dyekjær Madsen
Asynkron VLSI design:
8-transistor delay-insensitive memory cell (engelsk).
An asynchronous processor (engelsk).
Some processor background, preliminary (engelsk).
(High Speed Processor, delay<ns per instruction (GHz)).
Master project:
Two phase.
Bridge rectifiers in CMOS.
Example of part of master project containing standard CVSL logic.
Elektronik:
How to make PIC's with high clockspeed.
Hardware simulator for Turbo Pascal (engelsk).
PIC16C84 Programmer (engelsk).
Tegnestifttastatur.
Z80 bootloader (engelsk).
Metastabilitet (engelsk).
20GB/sec. data seperator in 0.18µCMOS.
(30GB design)
Not aviable.
Andet:
Primtal / Multitasking.
Kalenderprogram.
PCB-layout utility.
Systems Without Memory
Running unknown look-up's
8751 ROM Monitor software
Z80 Bootload
Most PICs
Kursus synkron 4370
Easy 16C84
Extra lowcost
Analog phase detect
Internal multibit codeing for low power.
Analog low power converter
Simple+
EEprom
ISP
ISO
frq
PQ-Programmer
Refresh it
DRAM
|
CPU
Hardware Simulator
Very Old files
Links til andre servere:
Asynchronous Logic Home Page.
Asynchronous Processor Design.
Caltech Asynchronous VLSI Group.
The Event Controlled Systems Project.
Counterflow Pipeline Processor Architecture.
Avalanche Scalable Parallel Processor Project.
Andre links:
Klaus Hartnegg Pascal Page. Free pascal, BP7 compatible.
Electric VLSI CAD software. Just to run.
Satelitmodtagning af vejret!
Z80 homepage.
E-post adresse:
Gęstebog
.