It may be a problem with the delay in the decoders, which cause a spike on Vdd. One way to reduce it is to current limit it. Also synchronize it with a latch is possible.
With
non-inverted output, only using NMOS transistors, and
full-static design, is it possible to use the NMOS in series
to do pull-up, while other NMOS do pull-down.
It may be a problem with the delay in the decoders, which cause
a spike on Vdd. One way to reduce it is to current limit it.
Also synchronize it with a latch is possible.
Another is folowing NMOS design:
Output is Vt lower than Vdd, but it is enough for most
cases in RAM/ROM design because word select controls a
strong NMOS device. It should not control a CMOS input,
without a PMOS pullup feedback (a wPMOS to pull-up input
when output of the inverted input is low), but it may be
able to control some NMOS. Vdd and Gnd of the decoder may be
swaped around to invert outputs.
