8-transistor memory cell for asynchronous logic.

This cell is based on a standard 6-transistor static memory cell. The idea is to use three-state inverters instead of using normal inverters, and to write high values to the cell instead of low values. Verification is possible because it is possible to read when the negated output goes low.

The cell has a lot of advantages compared to other cells:

• No problems with destructive read when transistors have been properly sized.
  ß(T4)=ß(T5) >= 4·ß(T1).
• High drive capacity.
• Low sensitivity of Vcc. The cell acts dynamic when no Vcc is applyed.
• No transistors drives against each other during write operation. That means no spikes at Vcc to the cell.
• No spikes at I/O lines. It is possible to use sense amplifiers.
• The cell is static, but the content of none selected cells are kept dynamic through write operation. The cell is full static if low value of /Di.t and /Di.f > 0.5V.
• Only 8 transistors are used. Very compact design. The size is only 27.5·19.5 µm². (1µ ES2 process).