It is very easy to make a high-speed data seperator in CMOS:
It all depends on the setup time of the flipflop. If the flipflop have a setup+hold time of 0.03ns, then is it easy to make it for 10-30GHz. (Using a very fast cmos process.)
But not all flipflops is that fast: Typical, they go into a "random" state, in the area around the time where it is latched. That may even depend on the last state of the flipflop. However, using a differential flipflop may store precise enough, and "erasing" the previos state using precharge makes it more independend of last state.
The idea is, that if any state before is resat, and if voltages etc. is total stable, including all inputs, then it will be able to control the place dependend of the value, but if it works differential, and the flipflop is symertic, should it be independend of the signal value (same place at 0 value, and 1 value). Another problem, is to make a very fast sample, that ensures that the previos value is not sampled - else it works as it samples an "average" value between the previos bits, and the next. Typical, CMOS is able to have a very high falltime, using dynamic precharge, or truely sized inverters.
The flipflop above do not absolutely work at very high speed. Using a low speed - multiple phase sample, allows high speed.
The PLL:
The data seperation need to be done with a digital PLL. Typical this kind of PLL is made using a multiple phase signal as above, but sampling at an even higher speed. (It is not a problem to have exact short delays between clocks. Also below inverter delay is possible. But the "maximum speed" must not be above the speed that it works for.)That means, that a lot of flipflops, will sample at a very high speed - also above the sampled signal rate. Lot of the flipflops will not have their hold time keeped, and they may be in a meta stable state. But that is not a problem.
Some of the flipflops will always sample the right signal. And then the task is to take output from a flipflop.
If you calculate, that you should sample at 5 times the sampled signal rates (may be above 100GHz. - imagnine) - then you just do it! Not problem to generate delay precise.
And your over 100 flipflops will still work at a lower frq. (may be below 1 Ghz!)
How to find the digital output: You may calculate that you need the output from the flipflops with a step (space) that is not full integer. If you as example need to step with 2.4 (calculate from the signal) then you need to step with 2, 2, 3, 2, 3, 2, 2, 3, 2, 3. Since you oversample the signal, is it precise enough. (It does not cause more than 20% error on time if you sample at 5 times the sample speed of the signal, and that is nothing compared to the hold+setup time)
The metode to calculate two or three samples is easy: If you have a remainder of 0.4 then e.g. multiply by 65536, and use the value to add in a sum machine. Every time it give an carry, you need to set the bit. Or use the high bit (above eg. bit 16)
See also how I do in my programmer for PIC's. Here the same idea is used generate the analog voltage on the RS232 output.
As the methode above shows, is it easy to make a digital PLL: It is much more precise then an analouge PLL. It works at any high speed, even above the maximum speed of the chip. (using multiple phases at lower speed to the PLL.) Since the oscillator that generates it, not need to have its frequence stabilized, is it easy to make stable using a stable voltage. And it will never need an "external" capacitor to "hold" the frequence for long time.
All the signals are periodic, why it should work, independend of any timekeeping kapacitors. Also, digital PLL's are easy to adjust fast: They can be precise programmed with the precise number (e.g. 2.344) to step. And that number may be calculated by a division each time to adjust: That means none delay. Sometime it is enough to synchronize the dataseperator with the data using the signals from some of the flipflops not used directly. (All signals is reprecented, as on a scope.)
The "digital" PLL may be used if the data sequence contains a lot of zeros, and that it is impossible to synchronize (synchronous operation). On asynchronous environtment, will it be possible to find some data, and here may it be enough to find some synchronization signal to "trig" on.
Also the sender, may be used with very high precise frequence using the "digital frequence synthesizer". Also here, will it be possible to use very close signals (sometimes random) to choose from. Then is it possible to generate a signal much more close to the ideal, than any analouge frequence generator do. Random calibration may be invalid.
