CMOS level converting using standard CVSL logic and DMOS transistors:

Standard static logic CVSL as level converter:

With standard split gates to reduce gate voltages:

Simple design without NMOS function block, for voltage convertion only. Disadvance is not to use NMOS transistors, and not have NMOS characteristics at inputs.

V1 and V2 regulates maximum voltages on some DMOS gates, and also voltage across Q1 and Q2 cross coubled P-FET's. If the maximum gate-source voltage of PDMOS is Vgsmax(PDMOS) then V1 must be above Vdd-Vgsmax(PDMOS), to avoid higher voltage at Vgs than Vgsmax-Vtp. Instead of using weak P-FET's is it possible to reduce the current by using a voltage on V1, that is some part above the critical. The selected current must be lower than the current, that is drawn low by pull-down path's. If the pull-down path is capable to pull 1mA, any lower current is used. One choise may be to select I=0.5mA, to make maximum current aviable for both low to high and high to low change. However, any lower current typical may be used, to avoid spikes on Vdd.

V2 must be below Vdsmax(NMOS), to avoid higher voltage at Vds(NMOS) than V2-Vt(NDMOS). It must be high enough to make sure that the current it is possible to pull low, is higher than e.g. 0.5mA.

Generation of V1 to reduce current, instead of using weak P-FET's:

Extra output buffer:

Extra output buffer with latch:

The level converters may be used to convert low voltage CMOS signals to high level signals.

With higher drive, if not weak PDMOS fet's.
V3 is lower than V1 to allow higher voltage on output drivers gate. Minimum voltage is Vdd-Vgsmax(PDMOS)-Vt. V2 is as before.