Four phase clocked phase detector:

Ion selects the active current, and charges C1..C4. Res resets the capacitor with the NMOS transistor. Keep, holds.

The outputs is calculated by comperator.

The outputs is proportional with time of cycle of previos two states.

Using that algorithme, makes the phase detector stable due to variations of phase. It need to be less than 2/3 of last to reset, or longer than 4/3 to change to high.

Analog detections and high accurance makes it works in a wide frequence spectrum.

If linear capacitors aviable:

Another bether idea is to have more "phase detectors" to generate both 2/3V and full V using 2/3*I as current for the "2/3" voltage. They are used to the comperators. Here, will not be importent to use matched different linear capacitors, since all capacitors is equal. (poly diff capacitors.) Simple versions of clocked differential amplifiers may be used. Outputs are digital.