The first rectifier, is made with four N-MOS transistors. It does not have any substrate current. It have low voltage drop, and it only uses NMOS transistors, and not any parasitic diodes. Only the two upper transistors need to be wide. (Lower two, is either opened or closed, and could be small - operates digital.)
A typical rectifier, with two diodes, that could be implemented in normal CMOS, using parasitic diodes:
The rectifier diodes, should be replaced by PNP transistors, in a normal CMOS process, with N-well's, and P-fet's in wells. (using P-substrate)
From my project.
The PNP transistors, is parasitic transistors that occeurs because the layers P-N-P+ (CBE), that work as an emitter followers. P (Collector) is always connected to Gnd (substrate). N (Basis) is N-Well, and P+ (emitter) is P diffussion in N-well. A NPN transistor arrives to surroundings, but a grounded N-well is good to shield surroundings.
All rectifiers are good - and have very low substrate current - first have ideal none. Also, the first may be easy to calculate on, because it does not involve parasitic BJT's. It may have some substrate current, and should also be shielded, with a surrounding grounded N-well, as the other, because of capacity. The version with P+NP transistors, and cross coubled P-transistors, do not have troubles with the N-well as substrate for the P-transistors, but current is injected into the substrate, and need to be collected with an grounded N-well. If all electrons is collected to ground is the "diodes" to ground almost ideal. General, is diodes (lateral) to ground most efficient, and diodes (lateral) to Vdd almost "impossible" or just "bad".
I used the last bridge in my project, with two N+PN transistors, each shielded with two big N-well to ground arround it, so that the substrate current was without any much influence and the voltage drop still low, because of using "bipolar transistors, in CMOS". But that may be a bad decision.
The reson for that decision, and not the first with 4 NMOS was the lower voltage drop on BJT diodes (only 0.5V - 0.6V) compared to older N-FET's. And the NMOS need to be very big to get that low voltage drop only. Today, I may change the decision, because that it is more simple to have good models for N-FET's than for the parasitic bipolars and voltage drop not be as importent. But it should however be much less than 1V, and the N-MOS transistors need to be very wide.