*----- +V2
!
I-I
I I R2
I-I
!
*--------------* Vc
! C1 !
Q /--!--\ --------- +
! ! ! --------- -
*---!---!-- ! !
! ! \!/ ! 0V
I-I \--!--/
I I R !
I-I ! Vp --- ---
! ! I I I I Pulses
*-------*------- 0--- ------- ---
|
When the voltage across Vc is higher than the pulses is
there no discharge of the capacitor C1 and the voltage
across it is pulled high by R2. When V(C1) is pulled to a lower
voltage than Vp-Vd will the base collector diode go
into saturation. This increases the capacity between
base and collector and the saturation-capacity will pull up
base at the time where the emitter goes low. Then C1 is
discharged to about the voltage Vp-Vd. And the voltage is
held low due to the repeating process.
Now you have a latch. |