Also example of no self timed (delay insensive) divider/asynchronous counter and asynchronous gray counter.

Changing one-phase clock to two phase - at half clock frequence. (simple.)

The sender sends Q1 and Q2 to the reciever, that removes noise. Q1 and Q2 is half clockfrequence of orginal clock, and reciever also restores orginal clockfrequence.

The C-ellements is flipflops that is reset in case of 00 at inputs, and set in case of 11 at inputs. In other cases is its state unchanged. The noise is removed with two c-elements restoring two phase clock, and xor'ed to generate double clock without noise. Mostly, I prefer to use double trigged two phase dividers and keep them delay insensitive (no selftimed parts). Selftimed parts often are sensitive to Vdd noise, and also bad practice compared to two phase clocking. (Single phase, need decoubling, voltage stabilizeing etc. just to make it work! However very popular, mostly because most people are without education and uses tools as VHDL that only allow this bad practice without warning. Then they often size and adjust transistors just to make a bad digital design practice work - even that it is proven to be sensitive. It uses very few transistors extra to make delayinsensentive two phase flipflops, less than 20%-50% extra. However, they will never contain delay sensitive parts, or self-timed parts in good flipflops.) I will say that good analog designers are allowed to use self-timed parts, oscillators, and self-timed flipflops. PLL's etc. They are able to handle voltage stabilize on chip, and even adjust voltages and RC delays by digital trimmed components using D/A converters, current regulators etc. (A current regulator need a stable voltage on chip, bandgap refference etc.) Also metastable free components using smith-triggers are analog.

It is possible to use Q1 and Q2 for two phase clock internal in the chip. But if the frequence is too slow, then it may be doubled by using double edged DFF's with two phase clock, to get orginal clock speed, or with single clock to get the double frequence of orginal:

Double-edge flipflop: (for higher internal speed)

Memory cells operate differential and is more roubust to Vdd because they keep data dynamicly when Vdd is zero.

Princip circuit for a two phase asynchronous ribblecounter, without load and enable inputs.

Standard two-phase counter with two phase outputs: (standard ribble counter, transistors)

E1 and E2 is enable and is high for counting. Ld is for loading data to the DFF. D1 and D2 may be different for gray and binary counting (outputs at slave flipflop is binary, while outputs at master flipflop is gray counting. Inverted outputs counts down, for gray outputs too.) At gray counting is D2=/D1 at load, while it for binary is equal.

Gray counting may be used for a lot of applications, as decoders, some places to avoid hazard, or to perform fewer changes of bits. (The average changes of bits is half than when counting binary one way round, and it is only one change per. bitline at the time, which reduce spikes in some cases as decoding.)

The graycounter was invented by gray, etc. It has been shown that it have only one bit that changes, for each number it counts.

Some counters above was a part of my M.Sc. (Developed to be noise immune and also work without Vdd.) Figure shows.